Nevertheless, during the bonding operation, particles may remain at the bonding interface. These particles will tend to be “coated by the bonding” but in the presence of thin layers (<100 nm), typically fully depleted silicon-on-insulator (FDSOI) substrates, the thickness of the semiconductor layer made of silicon Si of which is comprised between 5 and 20 nm and the thickness of the buried oxide layer, commonly denoted the “BOX”, of which is comprised between 10 and 200 nm, these particles may lead to breakages (holes) when the structure is thinned. In the worst possible case, for an undeformable particle, a particle of 100 nm may lead to a hole of 1 mm.
These holes are particularly problematic for the sequential production of 3-D transistor structures in which the active zone (semiconductor layer, for example of silicon) of the upper level may be produced by direct bonding an oxidized FDSOI substrate (the thickness of the oxide possibly typically being comprised between 5 nm and 50 nm) on top of a lower transistor level.
To this end, FIG. 1a illustrates an example of an FDSOI transistor structure. This type of transistor is produced on a silicon-on-insulator (SOI) substrate corresponding to a structure formed from a stack of a silicon layer (of a few nm to a few tens of nm thickness) on a dielectric layer possibly of silicon dioxide and thus forming a buried BOX dielectric layer. The SOI substrate more precisely includes a bulk silicon substrate 100, the buried BOX layer 101 and a semiconductor layer 102, such as a layer of silicon for example, in which layer a channel, a source region and a drain region are produced. The channel is covered with a gate dielectric 103 that may possibly comprise a plurality of layers, on which dielectric the gate 104 is placed, dielectric spacers 105 also being provided on the flanks of the gate. A dielectric layer 106 covers all of the transistor, it may typically be a question of a nitride layer. All of the structure thus defined is encapsulated with a dielectric 107, possibly typically an oxide.
The structure defined above and encapsulated with an oxide is planarized via a chemical-mechanical polishing (CMP) operation (represented by a dashed line in FIG. 1a). The thickness of this oxide may vary from 30 to 150 nm (zone above the lower transistor), after the CMP processing operation, the thickness possibly typically being 300 to 400 nm before.
Another SOI substrate (bulk substrate 200, a buried BOX oxide layer 201 and a silicon semiconductor layer 202) oxidized beforehand so as to form an upper layer 207 is then bonded on top of the transistor structure defined beforehand. The two oxides are thus bonded, as illustrated in FIG. 1b, which shows the two assemblies intended to be bonded via the layers 107 and 207.
The bonded structure is then thinned: the bulk silicon is mainly removed by a planar grinding process or a milling operation (particular mechanical machining technique), then by chemical etching, typically in tetramethylammonium hydroxide (TMAH). The buried BOX oxide (thermal oxide), the thickness of which may be comprised between 10 nm and 150 nm, is then etched, typically with an HF-based chemistry, leaving uncovered the upper layer 202 of Si, as illustrated in FIG. 1c. 
It is important to note that the oxide forming the oxide layer 107 is a deposited oxide and therefore has a much lower resistance to HF than that of a thermal oxide such as the thermal oxide of the oxide layer 207 for example (it will be noted that the oxide layer 207 could also be a deposited oxide layer)—thermal oxide etches at a rate of 6 nm/min in HF diluted to 1%. Deposited oxides are for example consumed two times more rapidly. This point is very important because if a particle is inserted at the bonding interface and breaks the thin layers (207-202-201), the oxide of the lower oxide layer 107 of the lower level is “exposed” during the HF-based chemical etches used to remove the BOX, as illustrated in FIGS. 2a and 2b, which show a particle P trapped in a hole C during the operation of bonding the two assemblies, before and after removal of the bulk portion and before and after removal of the BOX layer. More precisely, breakage occurs during the thinning of the bulk portion, this effect being equivalent to a mechanical release, whereas just after bonding there is generally no breakage.
By way of example, a chemical removal operation for removing a BOX of 50 nm would be liable to create a hole C of more than 100 nm.
This effect is all the more problematic since the size of these bonding holes may continue to increase as and when they are subjected to the technological steps required to produce the upper level, and may reveal contaminating metal layers, for example layers of Ti/Al/La, etc., in the gate stack and layers of NiPtSi in the silicided zones. Before the formation of the contacts, the source and drain zones are silicided. This process consists in depositing a metal layer on the sources/drains and in heating to create an alloy, typically NiPt+Si=NiPtSi.
FIG. 3a illustrates this effect, in particular with the step of producing mesas for the transistor of the upper level (which in particular is represented by the second semiconductor layer 202, dielectrics 205 on the flanks and a gate oxide 204) which step is represented by an arrow referenced RP/TOP (for TOP recess process) and also by an arrow referenced RP/TOP level with the hole C. FIG. 3B illustrates the same effect, with the presence of metal line 300 allowing contact to be made to source/gate/drain elements.
A simple solution would be to dimension the lower structure so that it could “take” all the consumption associated with production of the upper level, as illustrated in FIG. 4 showing a large thickness referenced H of first oxide above metal lines 300 in the first oxide layer 107. However, this would be detrimental to the production of 3-D contacts 400, with a critical aspect ratio during the etching of these contacts and an increase in resistance (increased length of the line).
To solve the aforementioned problems and to prevent trapping of particles during the bonding of two stacks of layers from degrading these stacks by generating holes, the present invention proposes to use a process for “plugging” holes including producing plugs by depositing a layer of planarizing material then planarizing this planarizing material layer by selective etching.
Thus the objective that it is sought to achieve in the context of the production of transistor structures is to plug holes up to the level of the active zone formed by the second semiconductor layer 202 of the upper level in the fabricating process described above and in particular illustrated in FIG. 2a or 2b. The planarizing material layer must be planarizable above the upper active zone, while avoiding the use of a planarizing or chemical-mechanical polishing (CMP) technique. Specifically, CMP processes do not allow the planarization of holes larger than about one-hundred microns to be managed and may induce more defects.